1. Field of the Invention
The present invention relates to a digital data processing circuit in the form of a pipelined adder circuit.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a conventional carry ripple adder circuit comprising a plurality of full adders 1A.about.1I. A carry from the full adder 1A at a lowest bit position or LSB is passed successively through the full adders 1B, . . ., 1I. Each of the full adders 1A.about.1I has input terminals supplied with 1-bit data out of first data (A8, A7, . . ., A0) having a word length of 9 bits and 1-bit data out of second data (B8, B7, . . ., B0) having a word length of 9 bits. The full adders 1A.about.1I have respective output terminals for outputting 9-bit data (08, 07, . . ., 00) which are the sum of the first and second data. The data items A8, B8, 08 are MSBs, respectively. One carry propagating circuit for adder circuits is disclosed in Japanese Patent Publication No. 59-51022, for example.
The carry ripple adder shown in FIG. 1 operates at low speed as it requires a long processing time in which the carry is passed from the LSB to the MSB. A generalization of the carry ripple adder shown in FIG. 1 shows that an adder circuit for adding data having a word length of n bits (n is an integer of 1 or more) requires a processing time (delay time) corresponding to the processing times of n full adders for one adding operation.
FIG. 2 of the accompanying drawings an adder circuit which employs pipeline processing for the propagation of a carry for high-speed operation. Specifically, registers 2A.about.2H for holding data are connected between the carry output terminals of preceding full adders and the carry input terminals of following full adders. The pipelined arrangement is effective to delay input data more times for higher bits into timed relationship to the propagation of the carry. The adder circuit operates at high speed since it can add the data in a processing time that is equal to the processing time of one full adder.
If the input data are supplied to the adder circuit shown in FIG. 2 at a data rate that is equivalent to the processing time of three full adders, then the processing speed of the adder circuit becomes threefold, resulting in excessive specifications. As a result, the processing capability of the adder circuit cannot be fully put to use, and is wasteful.
To equalize the input data rate to the processing time of three full adders, the data may be transmitted as shown in FIGS. 3A through 3C of the accompanying drawings. In the system shown in FIG. 3A, data rows A, B, C, . . . each having a word length of 3 bits are successively transmitted over a single signal line. More specifically, if it is assumed that the 3-bit data rows A, B, C, . . . are indicated by A=(A2, A1, A0), B=(B2, B1, B0), C=(C2, C1, C0), . . ., respectively, then the data are successively transmitted in the sequence of A0, A1, A2, B0, B1, B2, C0, . . . one bit in a cycle over the signal line.
In the system shown in FIG. 3B, data rows A, B, C, . . . each having a word length of 6 bits are transmitted as data of high-order 3 bits and low-order 3 bits over two signal lines. More specifically, if it is assumed that the 6-bit data rows A, B, C, . . . are indicated by A=(A5, A4, A3, A2, A1, A0), B=(B5, B4, B3, B2, B1, B0), C=(C5, C4, C3, C2, C1, C0), . . ., respectively, then the data are successively transmitted in the sequence of A0, A1, A2, B0, B1, B2, C0, . . . one bit in a cycle over the first signal line, and in the sequence of A3, A4, A5, B3, B4, B5, C3, . . . one bit in a cycle over the second signal line with a delay of 3 cycles with respect to the first signal line.
In the system shown in FIG. 3C, data rows A, B, C, . . . each having a word length of 9 bits are transmitted as data of high-order 3 bits, middle-order 3 bits, and low-order 3 bits over three signal lines. More specifically, if it is assumed that the 9-bit data A are indicated by A=(A8, . . ., A1, A0), then the low-order bits (A0, A1, A2) are transmitted over the first signal line, the middle-order bits (A3, A4, A5) are transmitted over the second signal line with a delay of 3 cycles, and the high-order bits (A6, A7, A8) are transmitted over the third signal line with a further delay of 3 cycles. If it is assumed that the 9-bit data B are indicated by B=(B8, . . ., B1, B0), then the bits (Bj, Bj+1, Bj+2) of the data B are transmitted, following the bits (Aj, Aj+1, Aj+2) of the data A, over the signal lines. The bits of the data C are thereafter transmitted following the data B.
According to a generalization of the data transmission systems shown in FIGS. 3A, 3B, and 3C, data rows A, B, C, . . . each having a word length of n (n is a multiple of 3) can be transmitted in a time-division multiplexed fashion over n/3 signal lines. The data structure of the data rows is expressed by the following equations (1): EQU A=(An-1, An-2, . . ., A1, A0), EQU B=(Bn-1, Bn-2, . . ., B1, B0), EQU C=(Cn-1, Cn-2, . . ., C1, C0) (1)
where An-1, Bn-1, Cn-1 are MSBs and A0, B0, C0 are LSBs.
The data rows according to the equations (1) can also be transmitted in a time-division multiplexed manner over 2 .times.n/6 signal lines, as shown in FIGS. 4A, 4B, and 4C. FIG. 4A shows a data transmission system in which data rows A, B, C, . . . each having a word length of 6 bits are transmitted over two signal lines. FIG. 4B shows a data transmission system in which data rows A, B, C, . . . each having a word length of 12 bits are transmitted over four signal lines. FIG. 4C shows a data transmission system in which data rows A, B, C, . . . each having a word length of 18 bits are transmitted over six signal lines. Furthermore, data rows A, B, C, . . . each having a word length of n (n is a multiple of 4) can be transmitted in a time-division multiplexed fashion over n/4 signal lines.